The hardware implementation of lossless data compression is wildly used in big data computing and communication
since it combines the speed and power advantage of the dedicated circuit.This paper proposed a hardware compression circuit based on GNUzip(Gzip)lossless data compression algorithm.The dual Hash functions
parallel match processing
hardware storage oriented LZ77 compression data format and high-performance data adaptor were involved to accelerate the compression speed with the advantages of parallel calculation and pipeline structure.The hardware compression circuit
based on Verilog HDL
was tested and verified by field programmable gate array(FPGA).The test data shows that
compared with software implementation
the compression speed of hardware circuit is improved significantly while the compression rate is 65.9%.The average speed is up to 171Mb/s that can satisfy the real-time compression requests of network communication and data storage.