Among the existing reconfigurable block cipher hardware structures
the special instruction processor does not achieve high throughput rate
while resource utilization of the reconfigurable block cipher processing array is low and mapping process is very complicated.Therefore
the reconfigurable asymmetrical multi-core architecture (RAMCA) for block cipher was designed.Mapping processes of typical structures
which were SP (AES-128)
Feistel (SMS4)
L-M (IDEA) and MISTY (KASUMI)
was analyzed.Hardware implementation was designed and synthesized in a 65nm CMOS process.The experimental area is about 1.13sq mm while frequency reaches 1GHz.After the influence of the process is eliminated
the performance of RAMCA is higher than that of other special instruction processors and most of the reconfigurable block cipher processing arrays