Low Power Multistage Test Data Compression Scheme

CHEN Tian; YI Xin; WANG Wei; LIU Jun; LIANG Hua-guo; REN Fu-ji

doi:10.3969/j.issn.0372-2112.2017.06.015

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Low Power Multistage Test Data Compression Scheme

更新时间：2025-07-16

- Low Power Multistage Test Data Compression Scheme
- Acta Electronica Sinica Vol. 45, Issue 6, Pages: 1382-1388(2017)
- 作者机构：
  
  1. 合肥工业大学情感计算与先进智能机器安徽省重点实验室,安徽,合肥,230009
  2. 德岛大学, 日本德岛,770-8506
  3. 合肥工业大学计算机与信息学院,安徽,合肥,230009
  5. 合肥工业大学电子科学与应用物理学院,安徽,合肥,230009
  6. 德岛大学日本德岛,770-8506
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.61204046, No.61474035, No.61306049);Key Program of National Natural Science Foundation of China (No.61432004);New Teacher Fund of Special Research Fund for Doctoral Programs of Higher Education (No.2013JYXJ0650)
- DOI：10.3969/j.issn.0372-2112.2017.06.015
  CLC： TP391.76
- Published Online：25 June 2017，
  
  Published：2017
- 稿件说明：
移动端阅览
CHEN Tian, YI Xin, WANG Wei, et al. Low Power Multistage Test Data Compression Scheme[J]. Acta Electronica Sinica, 2017, 45(6): 1382-1388.
DOI：

CHEN Tian, YI Xin, WANG Wei, et al. Low Power Multistage Test Data Compression Scheme[J]. Acta Electronica Sinica, 2017, 45(6): 1382-1388. DOI： 10.3969/j.issn.0372-2112.2017.06.015.

摘要

随着集成电路制造工艺的发展，VLSI（Very Large Scale Integrated）电路测试面临着测试数据量大和测试功耗过高的问题.对此，本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理，以减少测试集中的确定位数量，之后再进行第一级压缩，即对测试向量按多扫描划分为子向量并进行相容压缩，压缩后的测试向量可用更短的码字表示；接着再对测试数据进行低功耗填充，先进行捕获功耗填充，使其达到安全阈值以内，然后再对剩余的无关位进行移位功耗填充；最后对填充后的测试数据进行第二级压缩，即改进游程编码压缩.对ISCAS89基准电路的实验结果表明，本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率，同时还能协同优化测试时的捕获功耗和移位功耗.

Abstract

With the development of the integrated circuit(IC) manufacturing technology

very large scale integrated(VLSI) circuits test is faced with the problems of over large test data volume and high test power consumption.This paper presents a low-power multistage test data compression scheme to address these two problems.Firstly

the proposed scheme preprocesses the original test set with the input reduction technology so as to reduce the volume of specified bits;secondly

the scheme compresses test patterns shifted in multi-scan chains according to their compatibilities and uses shorter code to demonstrate compatible test patterns

namely the first stage of compression;thirdly

the low power X-filling is conducted:X-filling for capture power reduction is first conducted for the unspecified bits to keep the capture power under the given threshold and then the remaining unspecified bits are filled for shift power reduction;finally

the proposed scheme further compresses test patterns using modified run-length coding.Experimental results for ISCAS89 benchmark circuits demonstrate that

compared with golomb

FDR

EFDR

BM code

etc.

the proposed scheme achieves better compression rate while reducing both the capture power and the shift power.

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