FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals

TANG Ran; WU Hong; ZHAO Ying-xin; MU Wei-wei; XU Xi-yan; MA Xiao-xu; LIU Bing; LIU Zhi-yang

doi:10.3969/j.issn.0372-2112.2017.09.010

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FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals

更新时间：2025-07-16

- FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals
- Acta Electronica Sinica Vol. 45, Issue 9, Pages: 2121-2126(2017)
- 作者机构：
  
  1. 南开大学电子信息与光学工程学院,天津,300350
  2. 天津市光电传感器与传感网络技术重点实验室,天津,300350
  3. 南开大学电子信息与光学工程学院,天津,300350
  4. 天津市光电传感器与传感网络技术重点实验室,天津,300350
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.61571244, No.61501262);Science and Technology Project of Tianjin Municipality (No.16YFZCSF00540)
- DOI：10.3969/j.issn.0372-2112.2017.09.010
  CLC： TP391
- Published Online：25 September 2017，
  
  Published：2017
- 稿件说明：
移动端阅览
TANG Ran, WU Hong, ZHAO Ying-xin, et al. FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals[J]. Acta Electronica Sinica, 2017, 45(9): 2121-2126.
DOI：

TANG Ran, WU Hong, ZHAO Ying-xin, et al. FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals[J]. Acta Electronica Sinica, 2017, 45(9): 2121-2126. DOI： 10.3969/j.issn.0372-2112.2017.09.010.

摘要

针对船舶自动识别系统（Automatic Identification System，AIS）中相邻多个小区的同频信号相互干扰、无法解调的问题，该文采用多天线接收混合信号，通过在FPGA上设计独立成分分析（Independent Component Analysis，ICA）算法来对混合信号进行实时盲分离.为满足实时性，文中用符号函数代替双曲正切函数对样点数据作非线性映射，简化迭代运算；并将样点数据分块存储，用于并行计算.同时实现了高精度特征分解（Eigen Value Decomposition，EVD），用于对混合数据进行白化.最后将设计的FPGA系统在Xilinx Isim中仿真，结果表明，主频20MHz时，系统在850s内完成了从4路512点AIS混合信号中分离出了三路源信号.本文的设计也可应用于雷达、声纳等可能存在同频干扰的实时信号处理系统.

Abstract

In order to demodulate the mixed co-channel automatic identification system (AIS) signals from neighbor cells

a multi-antenna receiver system is employed where the FPGA based independent component analysis (ICA) algorithm is implemented to separate the mixtures.To achieve real-time processing

we simplify the iteration formula by using sign function instead of hyperbolic tangent for nonlinear mapping

reducing the hardware complexity.Furthermore

a parallel iteration structure is adopted to improve the real-time performance.The paper also designs high precision eigen value decomposition (EVD) module to whiten the received mixtures.Finally

the FPGA design is simulated in Xilinx software platform Isim.Simulation results show that

when clocked at 20 MHz

the system completes separating 4 channels of 512 points mixed AIS signals within 850 s.This design can also be applied in radar

sonar and other real-time processing systems where co-channel interference may exist.

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