DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA

XUE Yi-ming; CHEN Yao; HE Ning-ning; HU Cai-e; WANG Jian-ping

doi:10.3969/j.issn.0372-2112.2018.03.027

您当前的位置：

首页 >

文章列表页 >

DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA

更新时间：2025-07-16

- DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA
- Acta Electronica Sinica Vol. 46, Issue 3, Pages: 695-701(2018)
- 作者机构：
  
  1. 中国农业大学信息与电气工程学院,北京,100083
  2. 北京中电华大电子设计有限责任公司,北京,102209
  3. 国网北京市电力公司,北京,100031
  4. 中国农业大学信息与电气工程学院,北京,100083
  5. 北京中电华大电子设计有限责任公司,北京,102209
  6. 国网北京市电力公司,北京,100031
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.U1536121)
- DOI：10.3969/j.issn.0372-2112.2018.03.027
  CLC： TN912.3
- Published Online：25 March 2018，
  
  Published：2018
- 稿件说明：
移动端阅览
XUE Yi-ming, CHEN Yao, HE Ning-ning, et al. DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA[J]. Acta Electronica Sinica, 2018, 46(3): 695-701.
DOI：

XUE Yi-ming, CHEN Yao, HE Ning-ning, et al. DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA[J]. Acta Electronica Sinica, 2018, 46(3): 695-701. DOI： 10.3969/j.issn.0372-2112.2018.03.027.

摘要

提出了WOLA（Weighted Overlap-Add）并行结构的低时延DFT滤波器组的设计和FPGA实现方法.为降低系统总体时延，在综合考虑传递失真、混迭失真的基础上，将群时延引入系统目标函数，并采用非对称综合原型滤波器设计方法，提出迭代算法，实现了DFT滤波器组低时延优化设计.通过对DFT滤波器组中分析和综合功能的关键模块采用多路并行乘法、多级流水加法链设计，实现了并行的WOLA结构DFT滤波器组，降低FPGA实现的计算时延.整个设计在Xilinx公司的Zynq7020型号FPGA芯片上进行实现.PESQ测试表明，设计的DFT滤波器组能取得较好的语音质量.与串行WOLA结构的实现对比表明，在16kHz语音采样率下，并行的WOLA结构FPGA实现的总时延能降低1.192ms，其中群时延降低12%，计算时延降低29.2%.

Abstract

A low-latency parallel WOLA (Weighted Overlap-add) DFT filter bank design method and its implementation on FPGA are presented. System objective function combined with group delay

asymmetric synthesis window design and iterative algorithm are adopted to reduce the overall system delay during the optimization of DFT filter banks. Calculation delay of FPGA implementation is controlled through multichannel parallel multiplication

multistage pipeline addition chain in key modules of DFT filter banks. The whole design is implemented on a Xilinx FPGA chip of Zynq7020. PESQ test shows that the design can achieve good speech quality. Compared with the serial WOLA structure

the delay of parallel WOLA can be reduced by 1. 192 ms at 16 kHz speech sampling rate

with the group delay reduced by 12% and the calculation delay reduced by 29. 2%.

关键词

Keywords

references

Views

367

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Operator Fusion Method and Hardware Architecture Design Based on Non-Standard Operators

Multi-Hop Clock Synchronization Algorithm and System Implementation Based on IEEE 802.1AS

An Improved Attention Mechanism Algorithm Model and Hardware Aceleration Design Method

Verification of FPGA Encryption Protection Design Based on Laser Injection

Design and Optimization of Target Detection Accelerator Based on Winograd Algorithm

Related Author

WANG Ying

GAO Lan

ZHANG Zhe

LIU Xin

WU Yi-xiong

ZHANG Wei-gong

ZHAO Guo-feng

WEI Rui-peng

Related Institution

College of Information Engineering, Capital Normal University

School of Mathematical Science, Capital Normal University

Faculty of Software Technologics, Shanxi Agricultural University

School of Communications and Information Engineering， Chongqing University of Posts and Telecommunications

College of Information Engineering， Capital Normal University

⁰