As the size of MOS device shrinks

the reliability effect becomes a prominent problem that limits the lifetime of the device.Negative bias temperature instability (NBTI) of PMOSFET is one of the key issues.NBTI degradation is closely related to the device geometry.In this paper

we investigate the NBTI effect of 65nm PMOSFET.By experiment

we obtain the dependency of NBTI degradation on device structure

and find that the NBTI damage of 65nm PMOSFET in this paper increases with the decrease of the channel width.By the method of defect charge analysis and TCAD simulation

we reveal the reason on the experimental result from the point of view of defect generation source and position.It is pointed out that the electric field and the defect charge in the shallow trench isolation (STI) region are the main causes of this phenomenon.The results provide a reference for device reliability design.