Dynamic Priority Arbitration Strategy for Interconnections of Hardware Spiking Neural Networks

doi:10.3969/j.issn.0372-2112.2018.08.014

您当前的位置：

首页 >

文章列表页 >

Dynamic Priority Arbitration Strategy for Interconnections of Hardware Spiking Neural Networks

更新时间：2025-07-16

- Dynamic Priority Arbitration Strategy for Interconnections of Hardware Spiking Neural Networks
- Acta Electronica Sinica Vol. 46, Issue 8, Pages: 1898-1905(2018)
- 作者机构：
  
  1. 广西师范大学电子工程学院,广西,桂林,541004
  2. ,四川,成都,611731
  3. 萨里大学萨里商学院商业转型和企业可持续性发展系, 英国萨里 GU27XH
- 作者简介：
- 基金信息：
- DOI：10.3969/j.issn.0372-2112.2018.08.014
  CLC： TP183
- Published Online：25 August 2018，
  
  Published：2018
- 稿件说明：
移动端阅览
Dynamic Priority Arbitration Strategy for Interconnections of Hardware Spiking Neural Networks[J]. Acta Electronica Sinica, 2018, 46(8): 1898-1905.
DOI：

Dynamic Priority Arbitration Strategy for Interconnections of Hardware Spiking Neural Networks[J]. Acta Electronica Sinica, 2018, 46(8): 1898-1905. DOI： 10.3969/j.issn.0372-2112.2018.08.014.

摘要

本文基于EMBRACE脉冲神经网络硬件实现方案提出了一种片上网络路由器的动态优先级仲裁策略，来解决脉冲神经网络脉冲传输的交通负载非均衡问题.该方案使用二维网格片上网络系统实现神经元之间的互连通讯，其基于脉冲发送频率的动态优先级仲裁策略能够降低高频路径的平均延迟及系统丢包风险，提高系统工作稳定性.使用Noxim片上网络模拟器搭建实验平台，测试结果表明采用提出的动态优先级仲裁策略较轮询及固定优先级仲裁器，高频路径延迟平均降低32.33%和34.69%，降低幅度最大达到84.86%和86.20%.在90nm CMOS工艺下，提出的路由器架构硬件面积为213，471m

，具有较好的扩展性.

Abstract

Based on the EMBRACE

i.e.a hardware architecture for the SNN

a dynamic priority arbitration strategy for a Networks-on-Chip (NoC) router is proposed to solve the non-balance traffic load problem of the SNN system.A2DmeshNoC system is used to provide the interconnected communication for the neurons.The dynamic priority arbitration strategy is based on the spiking transmission frequencies and it can reduce the risk of the packet loss and the average delay of the paths with heavy traffics

and improve the reliability of system.The Noxim simulator is used to build the simulation platform.The experimental results show that compared to the round-robin and fixed priority arbitration schemes

the proposed dynamic priority arbitration strategy has an average of 32.33% and 34.69%(maximum 84.86% and 86.20%) decrease for the delays of paths with heavy traffics.Based on the 90nm CMOS technology

the hardware area is 213

471 m

which demonstrates its scalability.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

A New Scheduling Algorithm with O Control Messages Complexity for High-Speed Crossbars

Survey on Distributed Control in a Router

Study on Router Buffer Size with NewReno Congestion Control Method

Related Author

ZHANG Jian-chong

LIU Yan-lin

LIAO Shi-wen

LING Guo-jun

HUANG Yi-hua

ZHAO Wen-dong

TIAN Chang

PENG Lai-xian

Related Institution

Department of Electronic and Communication,Zhongshan University

School of Information EngineeringUniversity of Science and Technology BeijingBeijing 100083China

Shijiazhuang Mechanized Infantry InstituteShijiazhuangHebei 050083China

Department of Computer Science and TechnologyTsinghua UniversityBeijing 100084China

School of Information Engineering,University of Science and Technology Beijing

⁰