BAI Wen-shuai, WU Jin, WU Dan-yu, et al. Background Calibration Technology for High Speed Time-Interleaved ADC Based on FPGA[J]. Acta Electronica Sinica, 2018, 46(8): 2020-2025.
DOI:
BAI Wen-shuai, WU Jin, WU Dan-yu, et al. Background Calibration Technology for High Speed Time-Interleaved ADC Based on FPGA[J]. Acta Electronica Sinica, 2018, 46(8): 2020-2025. DOI: 10.3969/j.issn.0372-2112.2018.08.030.
Background Calibration Technology for High Speed Time-Interleaved ADC Based on FPGA
Due to the time interleaved analog-to-digital converter (TI-ADC) existing three major mismatch error (the sampling time interval mismatch error
offset mismatch error and gain mismatch error)
a digital background calibration technique based on FPGA is proposed.The mismatch error can be obtained by the calibration algorithm
which is based on the mathematical method of statistical approximation.Feedback regulation is used to reduce the three major mismatch errors of TI-ADC.This technology adopts off chip calibration
calibration algorithm is completed in the FPGA
and the calibration control circuit is completed in TI-ADC.The experimental results show that the average effective number (ENOB) and the average spurious free dynamic range (SFDR) are improved by 0.58 and 11.28dBc respectively.The effectiveness of the proposed background calibration technique is verified.