The existing network data plane could not support the evolution and innovation of network functions

thus the new data plane technology for user-programmability is developing rapidly. For the huge amount of hardware resource costs and the lack of responsible resource optimization

a resource cost model combining parser

match table

and action processor is built

and the corresponding resource optimization methods like type field combination

match field offset combination and "field-to-word" mapping are proposed. The NetFPGA-based experimental results show that the proposed mechanism can reduce hardware resource cost by 38% compared to existing mechanisms.