SEU is one of the important causes for the microprocessor in which the exception occurs in space environment. SEU not only causes single-bit error

but does lead to a number of multi-bit errors

along with the reduction of the IC feature size. It is a great challenge that we find a way to effectively cope with the multi-bit error. This paper proposes a fault-tolerant method which backs up the pipeline registers based on cycle granularity

the dual modular redundancy is applied in this method. The pipeline registers on the two pipelines are compared through the comparators to detect the error and the pipeline registers are backed up based on cycle granularity. It takes two cycles to restore the error pipeline when the error is detected. The write buffer is set in the entrance to the data cache and register file to avoid dirty data flowing out of the pipeline. And we can ensure the data is correct through delay write. This paper implements the fault-tolerant method based on SPARC V8 processor and tests in the simulation environment. The simulation results shows that the CPU clock speed of the hardened processor in which the proposed fault-tolerant method is applied can increase 70% at most and the fault-tolerance of the SEU

SET and MBU is implemented with the limited area overhead.