Chip Process variations cause yield degradation after manufacturing. To improve yield

the sequential circuit buffer insertion algorithm for yield improvement of chips is proposed. The locations of buffers are determined by sequential circuit simulating chips after manufacturing based on Monte Carlo simulations. The proposed method not only maintains a good yield improvement

but also reduces area cost. By using ISCAS89 benchmarks and TAU 2013 circuits

the simulation results show that the number of inserted buffers is no larger than 1% of the number of flip-flops in the circuits

and the yield is improved up to 35.98%.