Through-Silicon Via (TSV) is prone to introduce resistive open and leakage faults during the manufacturing process

which will seriously affect the reliability and yield of 3D chips

so the pre-bond TSV testing seems necessary. Existing pre-bond TSV testing methods still have some problems

such as incomplete fault coverage

large area overhead and large testing time. To tackle these problems

an edge transition delay based pre-bond TSV testing method is proposed in this paper. This method mainly measures the variation of TSV delay caused by physical defects

and separates the rising and falling edges to eliminate the interaction between them. Firstly

the variation of rise-time delay is transformed into a pulse signal with corresponding width; then

the pulse width is measured by pulse width reduction technology; finally

the measurement results are extracted by the state of trigger and compared with the reference value of fault-free TSV. The experimental results show that the proposed method performs better than the existing methods in terms of fault coverage

and area overhead.