A reversible circuit synthesis method based on BED (Boolean Expression Diagram) is proposed. The proposed method utilizes a BED to represent a Boolean function

and synthesizes a reversible circuit through mapping BED nodes to reversible cascades. Using a gate library consisting of NOT

CNOT and mixed-polarity Peres gates

the proposed method constructs a locally optimal reversible cascade for each BED node by considering whether the values of the child nodes of this node will be used by subsequent reversible cascades. In order to improve the cost of the circuit synthesized from the BED of a function

according to the sharing of pairs of variables among products of the function expression

variable ordering for the BED is achieved by variable grouping. The proposed method is validated using a set of benchmark functions. The results show that the proposed method is time efficient. Compared to the existing reversible circuit synthesis methods using decision diagram as a representation model

the proposed method can improve the quantum cost of the synthesized reversible circuits for almost all of the used benchmark functions

and can also reduce the number of qubits and the number of garbage lines in many cases.