Aiming at the high energy-efficiency implementation of cryptographic algorithm

this paper proposed a coarse-grained reconfigurable cryptographic logic array structure named PVHArray. Based on the research of cryptographic algorithm operation and control structure features

adopted the reconfigurable array structure design method

this paper proposed the coarse-grained reconfigurable cryptographic logic array structure and its parametric model

which is mainly composed of pipeline variable coarse-grained reconfigurable computing units

hierarchical interconnected network and perio

dic-oriented distributed control network. In order to improve the energy-efficiency of the reconfigurable cryptographic logic array

this paper combined the cryptographic algorithm mapping results to determine the model parameters

and constructed a high energy-efficiency PVHArray structure with a size of 4×4. The chip area of PVHArray is 12.25mm

2

based on 55nm CMOS technology

and at the same time

cryptographic algorithm mapping is performed for PVHArray. The experimental results show that the proposed high-efficiency PVHArray structure can effectively support the mapping of block

stream and hash cipher algorithm. In the cipher block chaining (CBC) mode

compared with state-of-the-art reconfigurable cryptographic logic array REMUS_LPP

the performance per unit area has increased by 12.9% and the performance per unit power has increased by 13.9%.