Aiming at the problem of long test time and affecting test efficiency in integrated circuit testing process

a hierarchical dynamic adjustment method for integrated circuit testing process was proposed. The Bayesian probability model was established by counting the test failure rate of each test type and each test vector in the sample integrated circuit

and the testing process is hierarchically adjusted according to the probability of their hit fault. With the test progressed

the test data was collected continuously

the test failure rate of test type and vector were updated dynamically

and their loading order was adjusted synchronously. The experimental results showed that the proposed method could significantly reduce test time and improve test efficiency. Furthermore

the proposed algorithm is completely based on software

no additional hardware overhead

and can be compatible with the traditional integrated circuit testing process.