A 1.8Vpp 250MS/s Pipelined ADC with Low Harmonic Distortion

WU Ke-ke; SHEN Yu-peng; LIU Jia-rui; WANG Zhi-yu; MO Jiong-jiong; YU Fa-xin

doi:10.3969/j.issn.0372-2112.2020.11.021

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A 1.8Vpp 250MS/s Pipelined ADC with Low Harmonic Distortion

更新时间：2025-12-08

- A 1.8Vpp 250MS/s Pipelined ADC with Low Harmonic Distortion
- Acta Electronica Sinica Vol. 48, Issue 11, Pages: 2242-2249(2020)
- 作者机构：
  
  浙江大学航空航天学院,浙江,杭州,310027
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.61604128)
- DOI：10.3969/j.issn.0372-2112.2020.11.021
  CLC： TN432
- Published Online：25 November 2020，
  
  Published：2020
- 稿件说明：
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WU Ke-ke, SHEN Yu-peng, LIU Jia-rui, et al. A 1.8Vpp 250MS/s Pipelined ADC with Low Harmonic Distortion[J]. Acta Electronica Sinica, 2020, 48(11): 2242-2249.
DOI：

WU Ke-ke, SHEN Yu-peng, LIU Jia-rui, et al. A 1.8Vpp 250MS/s Pipelined ADC with Low Harmonic Distortion[J]. Acta Electronica Sinica, 2020, 48(11): 2242-2249. DOI： 10.3969/j.issn.0372-2112.2020.11.021.

摘要

采用40nm CMOS工艺设计了一款在250MS/s采样率下具有1.8Vpp满摆幅和低谐波失真性能的流水线ADC（Analog-to-Digital Converter）.针对传统源跟随器结构的输入缓冲器在大摆幅下驱动大采样电容时线性度恶化的问题，采用了改进型电流注入技术和漏端电压自举技术.ADC中实现采样和电荷转移功能的开关采用薄栅器件设计，其工作电压由片上LDO（Low Dropout Regulator）提供，在降低开关寄生和电荷注入的同时保障了器件的可靠性.测试结果表明，对于10.1MHz单音输入，该ADC在-1dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别为68.3dB、76.4dBc、-75.1dBc，在-1.57dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别达68.3dB、80.1dBc、-78.6dBc.

Abstract

This paper presents a 250MS/s pipelined ADC with 1.8Vpp full scale and low harmonic distortion implemented in 40nm CMOS. To reduce the large distortion of the conventional source follower when it drives a large sampling capacitor at a large swing

an improved current injection technique and a drain voltage bootstrapping technique were employed. Switches used for sampling and charge transfer in the ADC were implemented with thin-oxide devices to reduce the parasitic capacitance and charge injection. Moreover

on-chip LDOs were applied to provide safe supply voltages for these switches to protect thin-oxide devices from reliability problems. Test results show that with a 10.1MHz input

the ADC achieves the signal-to-noise and distortion (SNDR) of 68.3dB

the spurious free dynamic range (SFDR) of 76.4dBc and the total harmonic distortion (THD) of -75.1dBc at -1dBFS

and it achieves 68.3dB SNDR

80.1dBc SFDR and -78.6dBc THD at -1.57dBFS.

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