1. 中国科学院微电子中心,北京,100029
2. 中国科学院半导体所,北京,100029
3. 中国科学院微电子中心北京,100029
4. 中国科学院半导体所北京,100029
纸质出版:2001
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刘新宇, 孙海峰, 海朝和, 等. 高速全耗尽CMOS/SOI2000门门海阵列[J]. 电子学报, 2001,29(8):1129-1131.
LIU Xin-yu, SUN Hai-feng, HAI Chao-he, et al. A High Speed Fully Depleted CMOS/SOI 2000 Gate Sea-Of-Array[J]. Acta Electronica Sinica, 2001, 29(8): 1129-1131.
本文对全耗尽CMOS/SOI 2000门门海进行了研究
阵列采用宏单元结构
每个宏单元包括2×8个基本单元和8条布线通道
其尺寸为:92μm×86μm.2000门门海阵列采用0.8μm全耗尽工艺
实现了101级环形振荡器和4~128级分频器电路
在工作电压为5V时
0.8μm全耗尽CMOS/SOI 101级环振的单级延迟为45ps.
Fully-depleted CMOS/SOI 2000 gate sea-of-array are described in the paper.The structure of macrocell is used
Including 2×8 basic cells and eight channels
with size is 92μm×86μm.The SOG(Sea-Of-Array) were developed with 0.8μm Fully-depleted CMOS/SOI technology.Some frequency dividers and ring oscillators are built on it.Unloaded 101 stage 0.8μm fully-depleted ring oscillators reported here have very good speed performance.Under 5V supply voltage
the delay per stage reaches 45ps.
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