ASIC(FPGA)+DSP+RAM is a popular model in high speed parallel pipeline signal processing.It is especially suitable for China.Based on the combination of FPGA's configurable logic blocks and external memory

the problem exist between limited PCB size and huge memory space is solved in radar data processing.On the other hand

the parallel pipeline functions of FPGA resolve the problem between mass radar data real-time processing and limited DSP speeds.The track correlation processing after using FPGA

FPGA's operation model control

data communication and exchange between DSP and host computer are all done by DSP.Therefore the optimal system structure is established.The system has been checked and accepted

and satisfies the requirement of the design.