In a single-stage multi-bit ∑-Δ modulator

the implementation of the multi-bit quantizer is often size and power consuming.When the bits of the quantizer increase

the scale of the circuit increases exponentially and soon becomes practically impracticable.In this paper

a new architecture

Noise-Reducing Loop

is proposed.It employs a quantizer with only a few bits and achieves much better performance that can only be achieved by using a huge quantizer in the conventional structure.Accompanied with the Dynamic Quantization algorithm

the modulator can trace the change of the input signal and achieve the near optimal performance adaptively.