In this paper

we propose a novel buffer insertion theory for clock delay and skew minimization.Based on the Elmore delay model

buffer to buffer delay is a convex function of buffer positions in a clock tree.The optimal buffer placement for delay minimization is achieved when all delay functions have the same derivative values.The minimal skew can be obtained by equalizing delay functions of different source to sink paths.For a given clock routing tree

we initially insert the same level of buffers in all the source to sinks paths

then minimize the clock delay by optimizing buffer positions

and minimize skew by simultaneous buffer level augment and buffer sizing.