An expandable BP on-chip learning neural network chip is designed and fabricated with a standard 0.6 μm CMOS technology.It includes 8 neurons and 64 synapses.A novel expanable topology is proposed so that no additional neuron error computation chip is needed to construct a whole neural network system.A neural network with L-layers can be composed by cascading L such chip.Analog circuits are used in this chip and capacitors are adopted to store weight values.The on-chip learning itself can be used as a refreshable tool to keep weight values right.The experiment of the parity check demonstrates the on-chip learning ability of the neural network chip.