YH TS-1 is a 32-bit embedded microprocessor designed by School of Computer in National University of Defense Technology.It is a top-down design and has fully intellectual property.YH TS-1 has a RISC core

six-stage pipeline

separated data Cache and Instruction Cache.Specially

YH TS-1 has dynamic instruction schedule with two instruction fetch units

vector processing mechanism towards embedded application

content copy/switch based register window interrupt processing mechanism

and support of the open WISHBONE IP interface specification.This paper will mainly describe the YH TS-1 RISC core design methodology and its critical implementation technologies.The experimental results will also be given at the end of the paper.TS-1 has been implemented and verified in Altera's FPGA EP20K400EBC

and the clock frequency can be 36.7MHz.