A real-time parallel array architecture is proposed to perform the forward and inverse discrete wavelet transform (DWT) by using lifting scheme for the filters recommended in JPEG2000.It consists of two row processors and one column processor.The signals are processed in parallel way.Multiplications are substituted for shift-add operations.The whole architecture is optimized in the pipeline design way to speed up and achieve higher hardware utilization.It performs a decomposition in approximately

N

2

/2

clock cycles for an

N×N

image.A compact and independent IP core based on the architecture for JPEG2000 VLSI implementation has been demonstrated in FPGA.