For VLSI designs under deep submicron technology

it is well known that interconnect delay has become dominant factor in determining the overall circuit performance.Buffer insertion is an efficient technique for interconnect optimization.This paper presents an algorithm of routing and inserting buffers simultaneously to reduce wire delay for a two-pin net under fixed buffer locations based on accurate delay models.Given a two-terminal net

the algorithm can not only minimize the total delay time of the net

but also minimize the number of buffers inserted to meet a given delay constraint

thus avoid needless power and area cost.