A new architecture for reconfigurable coprocessorr proposed

refers to as DReAC (Dynamically Reconfigurable Array Coprocessor)

which is much helpful for the parallel data processing or the high density computation.DReAC consists of a reconfigurable computing array

a data-cache array and a global control unit.DReAC is able to work in parallel mode or pipeline mode.A behavioral model which was used in simulation algorithms was briefly introduced in this paper.The simulation results show that DReAC achieves much higher performance with 10x factor

comparing with traditional processors and some others reconfigurable processors.