HE Xiao-wei, CHENG Liang, JI Rong, et al. Design of 50% Duty-Cycle Correction Based on Phase-Blending[J]. Acta Electronica Sinica, 2007, 35(8): 1572-1576.
HE Xiao-wei, CHENG Liang, JI Rong, et al. Design of 50% Duty-Cycle Correction Based on Phase-Blending[J]. Acta Electronica Sinica, 2007, 35(8): 1572-1576.DOI：
A high performance 50% phase blending duty-cycle corrector(PB-DCC)
designed with a purely digital phase-blending technique
is presented in this paper.The novel features of the proposed DCC include a higher reliability against process
voltage and temperature(PVT) variation due to the use of the synchronous mirror delay(SMD) technique
no-skew output clock
and much faster duty-cycle correction speed compared to conventional DCC's.When designed with a 0.13 m CMOS technology
the HSPICE simulation indicates that the acceptable duty-cycle of input signal ranges from 10% to 90% when the clock frequency is 400MHz and the correction operation spends only 4 clock cycles with output duty-cycle varying from 48% to 52%.
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