As feature size shrinks and the frequency increases

power dissipation has become the main restriction on micro-processor design.The traditional power controlling policies for instruction cache (I-Cache) are used for reducing the dynamic access power or the leakage power respectively.Two improved power controlling policy are proposed to reduce the dynamic and leakage power at the same time more efficiently.One is called "Multi-Way Way Prediction (MWWP) policy with a Two Prediction-ports Way Predictor (TPWP)" that is proposed for the case of keeping the original level of the front-end pipeline stages.The other is called "Phased cache with On-demand Wakeup Prediction

(POWP) policy" that is proposed for the case of allowing new stage is inserted into original front-end pipeline.The research results show that:compared with traditional power controlling policies

proposed policies have the better power efficiency.They can reduce the power of whole processor more efficiently with less performance degradation.