A charge self-compensation techniques

based on the dynamic node of the P-type charging dynamic node of N-type

is proposed in this paper.Utilizing this technique

the dual-threshold voltage techniques and the multiple supply voltages techniques a low power and high performance Zipper CMOS domino full-adder is designed.And a novel method of the power distribution is introduced.With this method

the optimal path of the proposed Zipper CMOS full-adder with the charge self-compensation techniques is found accurately to minimize the power.Simulation results prove that active power of proposed Zipper CMOS full-adder can be reduced by up to 37%

5% and 7%

and static power can be reduced by up to 41%

20% and 43% as compared to the standard

the dual threshold voltage

and the multiple supply Zipper CMOS domino full-adder under similar delay time

respectively.At last

the inputs and clock signals combination sleep state dependent on leakage current characteristics is analyzed and the optimal sleep state is obtained.