An Efficient Reconfigurable VLSI Architecture for H.264 High Profile Inverse Transform
电子学报2011年39卷第5期 页码:1072-1076
作者机构:
1. 北京大学微处理器研究开发中心,北京,100871
2. 北京大学深圳研究生院,广东,深圳,518055
3. 北京大学微处理器研究开发中心北京,100871
4. 北京大学深圳研究生院广东深圳,518055
作者简介:
基金信息:
DOI:
中图分类号:TP302
纸质出版:2011
稿件说明:
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陆晓凤, 刘锋, 佟冬, 等. 一种支持H.264 High Profile的高效可重构反变换VLSI结构[J]. 电子学报, 2011,39(5):1072-1076.
LU Xiao-feng, LIU Feng, TONG Dong, et al. An Efficient Reconfigurable VLSI Architecture for H.264 High Profile Inverse Transform[J]. Acta Electronica Sinica, 2011, 39(5): 1072-1076.
陆晓凤, 刘锋, 佟冬, 等. 一种支持H.264 High Profile的高效可重构反变换VLSI结构[J]. 电子学报, 2011,39(5):1072-1076.DOI:
LU Xiao-feng, LIU Feng, TONG Dong, et al. An Efficient Reconfigurable VLSI Architecture for H.264 High Profile Inverse Transform[J]. Acta Electronica Sinica, 2011, 39(5): 1072-1076.DOI:
H.264 High Profile proposes the new 8×8 integer transform which achieves average bit-rate reduction of around 10% for HD material.This paper presents an efficient architecture for H.264 multiple block-size inverse transform.2-D transform decomposition and common matrix operation extraction were applied to design general processing elements to simplify the implementation of transforms.The proposed architecture is both area-efficient (4807gates) and high performance (can provide real-time decoding of 4096×2048@60fps High Profile in 150MHz
1.2G pixels/s data throughput rate
using TSMC 0.13 μm).This paper supporting all of the H.264 high profile transforms is the most efficient one
compared with the existing designs with the Data Throughput rate per Unit Area (DTUA) adopted as the comparison index.