In this paper

an effective strategy of point multiplication scheduling and an improved algorithm of dual-field high radix Montgomery modular multiplication are proposed. Based on them

a new high-performance scalable public-key cipher coprocessor architecture for RSA and ECC computing acceleration is designed

which is implemented using the 0.18 μm 1P6M standard CMOS technology.The coprocessor has strong scalability and flexibility

which can support the modular exponentiation up to 2048 bit and the dual-field elliptic curve scalar multiplication up to 576 bit by enlarging the high-speed memory on chip and using the radix-length as processing base.The measured result shows that the coprocessor chip has high performance for accelerating the computation of RSA and ECC and can perform one 1024-bit modular exponentiation only in 197 μs

one the prime field 192-bit scalar multiplication only in 225 μs and the binary field 163-bit scalar multiplication only in 200.7 μs.