<FONT face=Verdana>Based on the research on S-box constitution algorithm of Advanced Encryption Standard

we use the periodical characteristic of affine transformation in S-box to improve the circuit architecture and propose an area optimized combinational logic S-box implementation of AES. We multiply the circuit frequency and reuse the circuit with the pipeline technology. The synthesis result shows that the new S-box functional unit not only decreases the area of byte substitution compared with traditional S-box combinational logic by 47.53% and 41.49% and with truth table S-box combinational logic by 21.43%

but also maintains the critical delay of the circuit. Using the unit-gate model approximations

the hardware gate count of S-box is 880 gates. And the S-box scheme is applied to the application specific instruction processor for cryptography which is tested on Altera’s FPGA Cyclone II EP2C20.