A RTL Level ODC Algorithm for Data Path Low Power Optimization
电子学报2010年38卷第7期 页码：1654-1659
作者机构：
浙江大学超大规模集成电路设计研究所,浙江,杭州,310012
作者简介：
基金信息：
DOI：
中图分类号：TN47
纸质出版：2010
稿件说明：
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FONT face, Verdana, 孟建熠, 等. 一种RTL级数据通路ODC低功耗优化算法[J]. 电子学报, 2010,38(7):1654-1659.
FONT face, Verdana, MENG Jian-yi, et al. A RTL Level ODC Algorithm for Data Path Low Power Optimization[J]. Acta Electronica Sinica, 2010, 38(7): 1654-1659.
FONT face, Verdana, 孟建熠, 等. 一种RTL级数据通路ODC低功耗优化算法[J]. 电子学报, 2010,38(7):1654-1659.DOI：
FONT face, Verdana, MENG Jian-yi, et al. A RTL Level ODC Algorithm for Data Path Low Power Optimization[J]. Acta Electronica Sinica, 2010, 38(7): 1654-1659.DOI：
<FONT face=Verdana>This paper proposes an efficient and low-overhead optimization algorithm for clockgating based low power design. It searches the Observability Don′t Care (ODC) conditions of data path at RTL level. It analyzes the ODC conditions of RTL logic level signal which is defined as Bus-ODC model. Data path is cut down into several short paths and computed ODC condition separately
which is defined as Path-ODC model. These two models can reduce the ODC computation load and improve the computation efficiency
and make it sufficient for VLSI low power optimization. Probability of ODC conditions is also proposed in this paper and used as an important basis of clock gating logic synthesis. It is preferred to insert clock gating logic into the data path with high probability of ODC condition. Probability driven clock gating logic synthesis improves the efficiency of clock gating network with tiny hardware overhead. Compared with the result of traditional ODC algorithm
computation load of RTL level ODC algorithm is only one-eight of that
power can be reduced by 12.35% and hardware overhead is cut down by 13.44% in average.
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