<FONT face=Verdana>This paper presents the design of a CAVLC encoder for H.264 featuring a highly parallel and double-level pipelined architecture. In order to overcome the speed bottleneck of one coefficient per cycle during scanning

the proposed design uses four-channel parallel processing instead of serial scanning. And the delays of all stages in the pipelined architecture are averaged by FIFOs

which achieves a high efficiency for the entire pipeline. The pipelined structure is also widely used in sub-modules for higher throughput. Based on 0.18μm CMOS technology

the proposed architecture is synthesized into 20685 logic gates and achieved average 27M blocks/s at 166.7MHz frequency

and even meets the requirements of real-time processing of digital cinema video (4096×2048@30fp). The date throughput of the proposed architecture is 3.46 times of that of the previous reported work with acceptable increase in area.