Memory subsystem plays a vital role in embedded systems.Since it’s hard to obtain increasingly capacity for traditional memory systems

NAND Flash based SSM (solid state memory)

especially heterogeneous SSM with RAM (read only memory)

is becoming more and more widely used.Corresponding to low speed problem in SSM

cache and parallel technologies are commonly used for optimization.However

it poses a significant challenge to integrate them into a single solution in most applications.This article presents a mechanism based on cyclic buffer and integrates caches with parallel technologies.Cache and Storage modules are connected through a switch-matrix.A unified buffer is introduced to handle errors.Benefiting from dual bus infrastructure

also flexible addressing and scheduling strategies

this approach can largely improve data level parallelism.Verification and empirical experiment results demonstrate the concept with high speed and satisfactory performance.Prototyping system shows the feasibility of the placement layout and routing within circuit board.