This paper presents a synthesis of synchronous dynamic sequential circuits （SDSC） in which capacitor is used as memory element instead of flip flop for double edge trigger.On the basis of theory of three essential circuits elements （signal

network and load）

the edge sampling theorem is derived first

then a Karnaugh map method is developed from gate stage into element stage and finally the state assignment principle for CDSC is presented

so that an efficient synthetic procedure of SDSC is formed.By the use of the synthetic procedures

we have designed some SDSC which structures are very simplified

such as that the error code detecting circuits consists of only 22 MOS transistors and 8421BCD 10 counter consists of only 31 MOS tramsisters.