The principle and implementation of a general parallel Cyclic Redundancy Code

or CRC computing are described in the paper.It is suitable for any generator polynomial and any parallel degree of generator polynomial between 1 and 32.Compare with Table Lookup Algorithm

it need not the high speed RAM which was used to store the remainder table

and decrease the delay.Thus

we can increase properly parallel degree to decrease the clock frequency of CRC computing in high speed digital systems.