we propose a neural learning approach for performance-driven partitioning on multichip modules. our method is unique in (1) allowing simultaneous design in logic and layout. (2) considering both logical relation between modules and physical structure of MCM.(3)having double optimal object
minimizing number of connections between chips and cycle time of system. (4) making connections occur between chips as close as possible. (5)making the structure of neural network reasonable and training speed rapid.