A novel idea is presented in this paper for the first time. The equivalent model of the interconnects in the VLSI circuits should be hierarchical. For the low level circuit designing

the interconnects should be treated as multiport networks with distributed parameters;for the high level module designing

they should be treated as logic elements. Based upon this idea

a table logic model of the interconnects in VLSI circuits is presented. Three major negative effects

namely

crosstalk

signal distortion and delay

’are all considered in this model. Numerical results show that this model is accurate and efficient. Besides

features of the algorithms for the fast calculation of the transient responses to multiple input patterns are also proposed.