An optimization-based synthesis method for analog circuits is proposed. The simulated annealing algorithm（SA） is employed to do topology selection and device sizing simultaneously

which overcomes the shortage of the traditional two-step synthesis mode. Moreover

an iteration strategy is composed to reduce the computational cost of SA. Taking this methodology

a synthesizer is developed which performs well in synthesizing many analog cells

such as simple amplifiers

current mirrors

operational amplifiers

analog multipliers and switched-power controllers

etc.