This paper presents a switch level fast timing simulator FTSIM to verify the logical behaviour and timing performance for MOS digital circuits of both prelayout and post-layout.Circuits are first partitioned into DCCs（DC-Connected Component）

then the charging and discharging of each output node of a DCC is modeled by a macromodel retaining the nonlinearity of transistors and its characteristic equation is computed by a voltage incremental technique.Besides

a heuristic eventdriven self-adaptive window algorithm is proposed to speed up waveform convergence when feedbacks present at DCC level.Testing results with benchmark circuits from industry show a speedup of 2 to 3 orders of magnitude over SPICE for medium scale circuits with typical 5% timing accuracy loss

and the speedup is nearly linear up with the circuit size.