The global spacing for BBL （Buildinq Block Layout） can improve the final chip layout quality. However

the global spacinq in 2-dimensions is a very complex and difficult problem. In this paper

an "annealinq" global spacinq algorithm is designed and speeded up by using several techniques so that the operatinq complexity is acceptable. The authors not only propose an idea about "channel density function of offset" to describe the dynamic channel wirinq density accurately when modules are moving

but also discuss how to keep the constraint graph constant by use of density function. Furthermore

the authors put forward "well-distributing the spare space" as an optimal aim for the global spacing so that overflows in detailed routinq caused by lack of channel capacity are eliminated and the optimizinq process is more effective. The experimental results show that the algorithm is practical and effective.