A new configuration of high speed parallel multiplier is presented. In this configuration

Wallace tree is used to simplify the modified Booth’s algorithm. Carry save adders

suitable for NMOS implementation

are used. In the last level of two bits addition

Manchester type adder with fast carry propagation is used instead of ordinary carry look -ahead adder. A new NMOS realization of Manchester adder is presented. The total gate count of this high speed parallel multiplier is less than that of the ordinary multiplier with modified Booth’s algorithm. The time of multiplicationis also reduced. Furthermore

the configuration of CSA array is much more regular. It is especially suitable for VLSI layout design.