The AND-OR gate

a main basic logic unit of the Multicell-Type Logic （DYL） which appeared in recent years

has further been studied and analysed. A JFET bias constructure has been developed. The mathematical expression of average propagation delay of an AND-OR gate is derived and the relation between transistor gain and circuit parameters is established. In addition

the physical factor causing the low level increase in cascade has been discussed

The experiments have been made by using washing emitter technique. Typical average delay per gate is o. 3ns and product of delay and power consumption is 2.1pJ. The experimental results and theoretical analysis indicate that the Multicell-Type Logic circuits are quite promising in high speed bipolar logic circuits.