The main problem in developing microprogrammable controlled high speed lest ipattern generator is that the pattern generating speed is limited by its instruction memory speed. Unfortunately

the speed of the memory which we adopt to build this instruction memory is never faster than that of the memory being developed. Therefore

the requirement on the pattern generator in testing high speed memories under development can never be met.We have designed a new instruction memory with an access time of only one AND-OR gate delay. It is suitable for the test pattern generator. Based on this principle

we have successfully developed our own microprogrammable controlled test pattern generator.This article describes the construction of two commercial semiconductor memory tester （Model BJ-1

Model QL-13）. It is followed by a brief discussion on a new pattern generator structure

namely

double handling construction. It seems that more benefits can be obtained from this instruction memory.