A new high speed integrated logic has been described. Instead of a single type of cell gate which is used in most logic IC’s

the new logic here described is based on several types of basic cells to synthesize a logic system. Therefore

the threshold characteristic will not be the common requirement for each type of cell gates. The main logic unit in DYL is a very high-speed linear AND-OR gate made with simple technology （without threshold）. A four-bit full adder carry chain specimen has been developed with wide-line photolithography. It’s time-delay measured for each carry stage is about 1 ns for the front edge of the signal and even much smaller for the trailing edge. The maximum power dissipation per gate is about 12.5mW. This new logic has been analysed and compared with several conventional integrated logic circuits.