In order to meet the application requirements of flexible interconnection in system on chip (SoC)

a 1.0625~10.3125Gbps multi-protocol SerDes circuit for software defined interconnection (SDI) system is proposed. The circuit uses a unified architecture to meet the requirements of different protocols. A 1×QPLL+4×Lane PLL structure is implemented to achieve the broadband data rate and the low jitter output. The 32dB channel loss compensation is achieved by programmable feed forward equalizer (FFE)

continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE) circuits. The output measures 21.2ps total jitter (TJ) and 633.7fs random jitter (RJ) RMS. The power efficiency of the test chip is 29.33mW/Gbps at 10.3125 Gbps. The output eye pattern of the transmitter

the jitter tolerance and the bit error rate of the receiver can meet the protocol specifications of FC-PI-4

RapidIO 3.0

10GBase-KR and 1000Base-X.