基于RISC-V的嵌入式多指令集处理器设计及实现
Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V
- 电子学报 2021年49卷第11期 页码：2081-2089
- 作者机构：
国防科技大学计算机学院，湖南长沙 410073
- 作者简介：
[ "成元虎 男，1996年出生，四川中江人.现为国防科技大学计算机学院硕士研究生.主要研究方向为微处理器体系结构. E-mail:chengyuanhu@nudt.edu.cn" ]
[ "黄立波（通信作者） 男，1983年出生，湖南邵阳人.现为国防科技大学计算机学院副研究员，主要研究方向为计算机体系结构. E-mail:libohuang@nudt.edu.cn" ]
[ "崔益俊 男，1995年出生，江苏东台人.现为国防科技大学计算机学院硕士研究生.主要研究方向为微处理器体系结构. E-mail:cuiyijun18@nudt.edu.cn" ]
[ "马 胜 男，1986年出生，湖南永州人.现为国防科技大学计算机学院副研究员.主要研究方向为计算机体系结构. E-mail:masheng@nudt.edu.cn" ]
[ "王永文 男，1977年出生，山东泰安人.现为国防科技大学计算机学院研究员.主要研究方向为微处理器体系结构. E-mail:yongwen@nudt.edu.cn" ]
[ "隋兵才 男，1981年出生，山东烟台人.现为国防科技大学计算机学院副研究员.主要研究方向为微处理器体系结构. E-mail:bingcaisui@nudt.edu.cn" ]
- 基金信息：国家自然科学基金(62090023;61872374)
DOI：10.12263/DZXB.20201350
中图分类号： TP302;收稿：2020-11-30，
修回：2021-03-03，
纸质出版：2021-11-25
- 稿件说明：
移动端阅览
成元虎,黄立波,崔益俊等.基于RISC-V的嵌入式多指令集处理器设计及实现[J].电子学报,2021,49(11):2081-2089.
CHENG Yuan-hu,HUANG Li-bo,CUI Yi-jun,et al.Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V[J].ACTA ELECTRONICA SINICA,2021,49(11):2081-2089.
成元虎,黄立波,崔益俊等.基于RISC-V的嵌入式多指令集处理器设计及实现[J].电子学报,2021,49(11):2081-2089. DOI： 10.12263/DZXB.20201350.
CHENG Yuan-hu,HUANG Li-bo,CUI Yi-jun,et al.Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V[J].ACTA ELECTRONICA SINICA,2021,49(11):2081-2089. DOI： 10.12263/DZXB.20201350.
摘要
软件生态是限制RISC-V指令集架构发展的主要因素之一.让RISC-V处理器可以直接运行ARM Thumb二进制代码能在一定程度上缓解其在嵌入式领域中的软件生态问题.本文基于二进制翻译，通过硬件支持ARM Thumb的标志位、分支指令、条件执行，在RISC-V处理器上以较低的面积和功耗开销实现了对ARM Thumb程序的支持并获得了较好的性能.通过运行Embench基准程序套件，该处理器翻译运行ARM Thumb程序的平均性能能够到达直接运行RISC-V程序性能的75.5%.相较于仅使用二进制翻译支持ARM Thumb，该处理器运行ARM Thumb程序的性能提升了3.1倍，面积开销则下降了7.8%.
Abstract
Software ecology is one of the most critical factors restricting the development of RISC-V instruction set architecture. Allowing the RISC-V processor to directly run the ARM Thumb binary code can solve its software ecological problem in the embedded field to a certain extent. Based on the binary translation
this article realizes support for the ARM Thumb program and achieves comparable performance on the RISC-V processor with the lower area and power consumption overhead by using hardware to optimize ARM Thumb flag bits
branch instructions
and conditional execution. For the Embench benchmark suite
the average performance of the processor running ARM Thumb programs can reach 75.5% of directly running RISC-V programs. Compared with using only binary translation to support ARM Thumb
hardware optimization performance is improved by 3.1 times and hardware overhead is reduced by 7.8%.
关键词
Keywords
references
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