3阶FLFB低通滤波器的最小可接受功耗分析

张旭东; 雷倩倩; 张芳玲; 李弦; 李连碧

doi:10.12263/DZXB.20210002

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3阶FLFB低通滤波器的最小可接受功耗分析

学术论文 | 更新时间：2025-12-08

- 3阶FLFB低通滤波器的最小可接受功耗分析
- Analysis of Minimum Acceptable Power Consumption of the 3^rd Follow-the-Leader-FeedBack Low Pass Filter
- 电子学报 2022年50卷第6期页码：1480-1486
- 作者机构：
  
  1.西安工程大学理学院，陕西西安 710000
  2.深圳市纽瑞芯科技有限公司，广东深圳 518000
- 作者简介：
  
  [ "张旭东男，1996年出生，河南平顶山人.西安工程大学在读硕士.研究方向为模拟基带有源滤波器.E-mail: 15202462872@163.com" ]
  [ "雷倩倩（通讯作者）女，1984年出生，陕西西安人.博士、副教授.主要研究方向为模拟、数模混合集成电路设计. E-mail: leiqianqian@163.com" ]
- 基金信息：
  
  深圳市科技计划资助项目(KQTD20190929172628244)
- DOI：10.12263/DZXB.20210002
  中图分类号： TN713;
- 收稿：2020-12-22，
  
  修回：2021-03-24，
  
  纸质出版：2022-06-25
- 稿件说明：
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张旭东,雷倩倩,张芳玲等.3阶FLFB低通滤波器的最小可接受功耗分析[J].电子学报,2022,50(06):1480-1486.

ZHANG Xu-dong,LEI Qian-qian,ZHANG Fang-ling,et al.Analysis of Minimum Acceptable Power Consumption of the 3^rd Follow-the-Leader-FeedBack Low Pass Filter[J].ACTA ELECTRONICA SINICA,2022,50(06):1480-1486.
张旭东,雷倩倩,张芳玲等.3阶FLFB低通滤波器的最小可接受功耗分析[J].电子学报,2022,50(06):1480-1486. DOI： 10.12263/DZXB.20210002.

ZHANG Xu-dong,LEI Qian-qian,ZHANG Fang-ling,et al.Analysis of Minimum Acceptable Power Consumption of the 3^rd Follow-the-Leader-FeedBack Low Pass Filter[J].ACTA ELECTRONICA SINICA,2022,50(06):1480-1486. DOI： 10.12263/DZXB.20210002.

摘要

对于多重反馈滤波器提出了一种最小可接受功耗的分析方法.采用劳斯-赫尔维茨稳定性判据对3阶FLFB（Follow-the-Leader-FeedBack）低通滤波器进行分析，当滤波器处于稳定临界状态时，利用MATLAB拟合出最小可接受相位裕度曲线和跨导图，通过电路级分析和验证，给出了滤波器设计参数与功耗之间的关系.采用UMC 40 nm CMOS 工艺进行电路设计，后仿结果表明：滤波器的带宽可调范围为0.9~9.9 MHz，版图面积0.03 mm

，此时总功耗为0.36 mW，与传统采用60°相位裕度的设计相比，功耗减小了近30%.在保证滤波器稳定工作的前提下，降低了功耗，与理论相吻合.

Abstract

An analysis method about the minimum acceptable power consumption of multiple-loop feedback filter is presented. When a 3

follow-the-leader-feedback(FLFB) low pass filter working at the stable state edge

based on Routh-Hurwitz stability criteria

synthesize the minimum acceptable phase margin curve and transconductance figure by MATLAB

and the relationship between filter design parameters and power consumption is given through circuit-level analysis and verification. Design is fabricated in UMC 40 nm CMOS technology

the post-simulation results show that the cutoff frequency is adjustable for 0.9~9.9 MHz

the layout area is 0.03 mm

and the total power consumption is 0.36 mW

reduced nearly 30% compared with the traditional design that phase margin is 60°. Under the premise of ensuring the stable operation of the filter

the power consumption is reduced

confirmed the minimum acceptable power consumption theory.

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references

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