结合测试点质量的混合测试点集合约简方法

欧阳丹彤; 许斌; 董博文; 周慧思; 张立明

doi:10.12263/DZXB.20210710

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结合测试点质量的混合测试点集合约简方法

学术论文 | 更新时间：2025-12-08

- 结合测试点质量的混合测试点集合约简方法
- Hybrid Test Point Set Reduction Method Based on Test Point Quality
- 电子学报 2023年51卷第6期页码：1552-1561
- 作者机构：
  
  1.吉林大学计算机科学与技术学院，吉林长春 130012
  2.符号计算与知识工程教育部重点实验室（吉林大学），吉林长春 130012
  3.吉林大学软件学院，吉林长春 130012
- 作者简介：
  
  [ "欧阳丹彤女，1968年出生于吉林省长春市.1998年毕业于吉林大学计算机科学系，并获博士学位.博士，教授，博士生导师.主要研究方向为自动推理与基于模型诊断.E-mail: ouyd@jlu.edu.cn" ]
  [ "许斌男，1997年出生于山东省枣庄市.目前就读于吉林大学软件学院.主要研究方向为基于模型诊断和测试诊断.E-mail: binxu19@jlu.edu.cn" ]
  [ "张立明（通讯作者）男，1980年生于吉林省榆树市.吉林大学博士.主要研究方向为基于模型诊断、可满足性问题和测试诊断." ]
- 基金信息：
  
  国家自然科学基金(62076108;61872159;61672261);吉林省教育厅科学研究项目(JJKH20211106KJ;JJKH20211103KJ)
- DOI：10.12263/DZXB.20210710
  中图分类号： TP306;
- 收稿：2021-06-04，
  
  修回：2022-05-24，
  
  纸质出版：2023-06-25
- 稿件说明：
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欧阳丹彤,许斌,董博文等.结合测试点质量的混合测试点集合约简方法[J].电子学报,2023,51(06):1552-1561.

OUYANG Dan-tong,XU Bin,DONG Bo-wen,et al.Hybrid Test Point Set Reduction Method Based on Test Point Quality[J].ACTA ELECTRONICA SINICA,2023,51(06):1552-1561.
欧阳丹彤,许斌,董博文等.结合测试点质量的混合测试点集合约简方法[J].电子学报,2023,51(06):1552-1561. DOI： 10.12263/DZXB.20210710.

OUYANG Dan-tong,XU Bin,DONG Bo-wen,et al.Hybrid Test Point Set Reduction Method Based on Test Point Quality[J].ACTA ELECTRONICA SINICA,2023,51(06):1552-1561. DOI： 10.12263/DZXB.20210710.

摘要

集成电路中插入测试点是芯片测试中不可或缺的环节，其方法是通过在电路上插入一定数量的测试点来提高芯片的故障覆盖率.集成电路测试是整个设计流程中不可或缺的关键步骤之一.为了进一步缩短测试时间和提高芯片良品率，越来越多的国内外学者们从事集成电路测试方法的研究.通过对插入测试点故障覆盖率的HTPI（Hybrid Test Point Insertion）方法深入研究，提出了结合测试点质量对测试点进行约简的RHTPI（Reduction of Hybrid Test Point Insertion）方法.此方法在保证故障覆盖率相等的情况下，有效提高了测试点选择的效率.从测试点覆盖率特征出发提出负质量测试点概念，依据负质量测试点对测试点集合进行约简，进而减小需要计算测试点集合的规模，有效缩短了求解时间.为避免负质量测试点删除部分具有较高覆盖率的测试点，提出了结合自适应系数的自适应负质量测试点的概念，依据自适应负质量测试点对测试点集合进行约简，进而在保证故障覆盖率相等的情况下有效提高了测试点选择效率.在标准测试用例上的实验结果表明，与HTPI方法相比，RHTPI方法计算候选测试点最小减少率为0.16%，最大减少率为44.56%，平均为24.56%，其求解效率最低提高了1.03，最高提高了2.37，平均提高了1.52，有效提高了测试点选择效率.本文给出的方法有效减少了芯片测试时间，进而缩短了芯片设计周期.

Abstract

Inserting test points into integrated circuits is an indispensable link in chip testing

the method of which is to improve the fault coverage of the chip by inserting a certain number of test points on the circuit. Integrated circuit testing is one of the indispensable key steps in the whole design process. In order to further shorten the test time and improve the chip yield

more and more scholars at home and abroad are engaged in the research of integrated circuit test methods. Through the in-depth research on the htpi method of inserting test point fault coverage

a RHTPI (Reduction of Hybrid Test Point Insertion) method for reducing test points combined with test point quality is proposed. Under the condition of ensuring equal fault coverage

the efficiency of test point selection is effectively improved. Starting from the coverage characteristics of test points

the concept of negative quality test points is proposed

and the test point set is reduced according to the negative quality test points

so as to reduce the scale of the test point set to be calculated and effectively shorten the solution time. In order to avoid deleting some test points with high coverage from negative quality test points

the concept of adaptive negative quality test points combined with adaptive coefficient is proposed. The set of test points is reduced according to adaptive negative quality test points

and then the selection efficiency of test points is effectively improved under the condition of ensuring equal fault coverage. The experimental results on standard test case show that

compared with htpi method

the minimum reduction rate of candidate test points calculated by RHTPI method is 0.16%

the maximum reduction rate is 44.56%

and the average is 24.56%; The minimum solution efficiency is increased by 1.03

the maximum is increased by 2.37

and the average is increased by 1.52

which effectively improves the efficiency of test point selection. The method given in this paper effectively reduces the chip test time

and then shortens the chip design cycle.

关键词

Keywords

references

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