面向多曲线的通用高性能ECC处理器设计
Multi-Curve-Oriented General High-Performance ECC Processor Design
- 电子学报 2023年51卷第6期 页码：1562-1571
- 作者机构：
1.哈尔滨理工大学，黑龙江哈尔滨 150080
2.清华大学集成电路学院，北京 100084
- 作者简介：
[ "刘志伟 男，1987年出生，哈尔滨人.现为哈尔滨理工大学测控技术与通信工程学院博士研究生.主要研究方向为可重构计算、高速密码算法、并行加密技术、密码芯片的安全设计等.E-mail: zwliu@hrbust.edu.cn" ]
[ "刘雷波 男，1976年生，新疆克拉玛依人.清华大学长聘教授，博士生导师，国家级一流本科课程负责人.主要研究方向为软件定义芯片、硬件安全和密码芯片、VLSI数字信号处理等.E-mail: liulb@tsinghua.edu.cn" ]
[ "黄海（通讯作者） 男，1982年生，内蒙古巴彦淖尔人.博士，教授，博士生导师，CCF高级会员.主要研究方向为信息安全、可重构计算、集成电路设计." ]
- 基金信息：国家重点研发计划“光电子与微电子器件及集成”重点专项子课题(2018YFB2202100);黑龙江省自然科学基金优秀青年项目(YQ2019F010);黑龙江省普通高校基本科研业务费专项资金(2019KYYWF0214)
DOI：10.12263/DZXB.20210967
中图分类号： TN492;TP309收稿：2021-07-26，
修回：2022-06-10，
纸质出版：2023-06-25
- 稿件说明：
移动端阅览
刘志伟,刘雷波,黄海等.面向多曲线的通用高性能ECC处理器设计[J].电子学报,2023,51(06):1562-1571.
LIU Zhi-wei,LIU Lei-bo,HUANG Hai,et al.Multi-Curve-Oriented General High-Performance ECC Processor Design[J].ACTA ELECTRONICA SINICA,2023,51(06):1562-1571.
刘志伟,刘雷波,黄海等.面向多曲线的通用高性能ECC处理器设计[J].电子学报,2023,51(06):1562-1571. DOI： 10.12263/DZXB.20210967.
LIU Zhi-wei,LIU Lei-bo,HUANG Hai,et al.Multi-Curve-Oriented General High-Performance ECC Processor Design[J].ACTA ELECTRONICA SINICA,2023,51(06):1562-1571. DOI： 10.12263/DZXB.20210967.
摘要
该文针对广泛应用的TLS1.3协议，提出了一种高性能的椭圆曲线密码处理器.该处理器支持TLS1.3协议中定义的两类素数域椭圆曲线的通用模数.通过对高基蒙哥马利算法的改进，提出了一种支持521 bit及以下位宽的模乘运算单元，并提出了一种双模乘单元并行结构的标量乘法器.基于该结构在两类椭圆曲线下设计了雅阁比坐标系下并行的点运算时序排布，使模乘单元的利用率在不同点运算情况下达到100%，95.4%和86.5%.与现有设计相比，本文中标量乘法运算消耗的周期更少，运算单元利用率更高，在相似的时间面积乘积前提下，具有更强的通用性和可配置性的优势.在TSMC 55 nm CMOS工艺下达到454 MHz的时钟频率，等效逻辑门数851k，Secp256r1曲线的标量乘运算速度为31 230 times/s.
Abstract
This paper proposes a high-performance elliptic curve cryptographic processor for the widely used TLS1.3 protocol. The processor supports two types of elliptic curve with general modulus in prime field defined in TLS1.3 protocol. Firstly
by modifying the high-radix Montgomery algorithm
a modular multiplication unit is proposed
which supports less than 521-bit width operators. Secondly
a parallel scalar multiplier structure with dual-modular multipliers is proposed. Based on this structure
to make full use of the two modular multipliers
a series of point operation timing arrangement is proposed in Jacobian coordinate
which supports two types of elliptic curves
makes the utilization rate of the modular multiplication unit reach 100%
95.4% and 86.5% under different types of point operations. Compared with the existing design
the scalar multiplier in this work has a less cycle cost and less time consumption
as well as stronger versatility and configurability with similar time-area products. Under TSMC 55 nm CMOS technology
the clock frequency reaches 454 MHz. The scalar multiplication costs 851k equivalent logic gates
and the calculation speed of Secp256r1 curve is 31 230 times/s.
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references
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